RISC-V Processor in a FGPA

For the Digital Design course I developed a project consisting in the implementation of a 32-bit RISC-V processor in a FGPA. From a simplification of the RISC-V instruction set I designed a 5-stage processor using Verilog as hardware description language and Vivado as integrated development and simulation environment.

I designed in Verilog a VGA and UART interface. The video shows a demonstration in which I pass a value from a computer through a serial communication and the processor displays this value on a screen. For this I wrote a simple program in machine language that reads a value from the serial terminal and displays it graphically through the VGA interface.